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ISL6219A
Data Sheet November 2002 FN9093
Microprocessor CORE Voltage Regulator Precision Multi-Phase BUCK PWM Controller for Mobile Applications
The ISL6219A provides core-voltage regulation by driving up to three interleaved synchronous-rectified buck-converter channels in parallel. Intersil multi-phase controllers together with ISL6207 gate drivers form the basis for the most reliable power-supply solutions available to power the latest industry-leading microprocessors. Multi-phase buckconverter architecture uses interleaved timing to multiply ripple frequency and reduce input and output ripple currents. Lower ripple results in lower total component cost, reduced dissipation, and smaller implementation area. Preconfigured for 3-phase operation, the ISL6219A offers the flexibility of 2-phase operation. Simply connect the unused PWM pin to +5V. The channel switching frequency is adjustable in the range of 100kHz to 1.5MHz giving the designer the ultimate flexibility in managing the balance between high-speed response and good thermal management. New features on the ISL6219A include Dynamic-VIDTM technology allowing seamless on-the-fly VID changes with no need for any additional external components. When the ISL6219A receives a new VID code, it incrementally steps the output voltage to the new level. Dynamic VIDTM changes are fast and reliable with no output voltage overshoot or undershoot. Like other Intersil multiphase controllers, the ISL6219A uses cost and space-saving rDS(ON) sensing for channel current balance and dynamic voltage positioning. Channel current balancing is automatic and accurate with the integrated current-balance control system. Over current protection can be tailored to any application with no need of additional parts. An integrated DAC decodes the 5-bit logic signal present at VID0-VID4 and provides an accurate reference for precision voltage regulation. The high-bandwidth error amplifier and accurate voltage reference all work together to provide better than 0.8% total system accuracy, and to enable the fastest transient response available. A window comparator toggles PGOOD if the output voltage moves out of range and acts to protect the load in case of over voltage.
Features
* Multi-Phase Power Conversion * Active Channel Current Balancing * Lossless current sense scheme - Uses MOSFET's RDS(ON) - Optional current sense method for higher precision * Precision CORE Voltage Regulation - 0.8% System Accuracy Over Temperature * Microprocessor Voltage Identification Input - Dynamic VID technology - 5-Bit VID Input - 1.100V to 1.850V in 25mV Steps * Programmable Droop Voltage * Fast Transient Recovery Time * Over Voltage, Under Voltage and Overcurrent Protection * Power-Good Output * 2 or 3 Phase Operation * User selectable Switching Frequency of 100K - 1.5MHz - 200KHz - 4.5MHz Effective Ripple Frequency
Ordering Information
PART NUMBER ISL6219ACA ISL6219ACA-T TEMP. (oC) -10 to 85 PACKAGE 28-Ld SSOP PKG. NO. M28.15
28 Lead SSOP Tape and Reel ISL6219A (28 LEAD SSOP) TOP VIEW
VID 0 VID 1 VID 2 VID 3 VID 4 NC FS/EN NC FB COMP NC NC NC GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC NC NC PGOOD NC ISEN1 PWM1 PWM2 ISEN2 ISEN3 PWM3 NC VSEN NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Dynamic VID is a trademark of Intersil Americas Inc
ISL6219A Block Diagram
PGOOD VCC
POWER-ON RESET (POR) VSEN X 0.83 + UV OV LATCH THREE-STATE CLOCK AND SAWTOOTH GENERATOR +
FS/EN
+ OV X1.15 -
-
+ PWM -
PWM1
SOFTSTART AND FAULT LOGIC
+
-
+ PWM -
PWM2
COMP +
-
+ PWM -
PWM3
VID0 VID1 VID2 VID3 VID4 DYNAMIC VID D/A
+ E/A -
FB
CURRENT CORRECTION PHASE NUMBER
CHANNEL DETECTOR
ISEN1 I_TOT OC + I_TRIP +
+ +
ISEN2
ISEN3
GND
2
ISL6219A Typical Application - 3-Phase Buck Converter
+5V VIN
VCC EN
BOOT UGATE PHASE
L1
RFB
RC
PWM1 +5V
ISL6207 DRIVER
LGATE GND
CC
FB
COMP VCC
+5V VIN
VSEN VCC BOOT UGATE PHASE L2
PGOOD VID0 VID1 VID2 VID3 VID4
ISL6219A
ISEN1 PWM1 PWM2
EN RISEN1 PWM2
ISL6207 DRIVER
LGATE GND
RISEN2 ISEN2 PWM3 FS/EN ISEN3 +5V VIN
RISEN3
P LOAD
L3
RT EN
VCC GND
BOOT UGATE PHASE
PWM3
ISL6207 DRIVER
LGATE GND
CO
3
ISL6219A Functional Pin Descriptions
VID0, VID1, VID2, VID3, VID4 (Pins 1, 2, 3, 4, 5)
These are the inputs to the internal DAC that provide the reference voltage for output regulation. Each pin has an internal 20A pull-up current source to 2.5V making the parts compatible with CMOS and TTL logic from 5V down to 2.5V. When a VID change is detected the reference voltage slowly ramps up or down to the new value in 25mV steps. Connect these pins to either open-drain or active-pull-up type outputs. Pulling these pins above 2.9V can cause a reference offset inaccuracy.
GND (Pin 14)
Bias and signal ground for the IC.
VSEN (Pin 15)
Power good monitor input. Connect to the microprocessor CORE voltage.
PWM3, PWM2, PWM1 (Pins 18, 21, 22)
Pulse-width modulation outputs. These logic outputs tell the driver IC(s) when to turn the MOSFETs on and off.
ISEN3, ISEN2, ISEN1 (PINS 19, 20, 23)
Current sense inputs. A resistor connected between these pins and the respective phase nodes has a current proportional to the current in the lower MOSFET during its conduction interval. The current is used as a reference for channel balancing, load sharing, protection, and load-line regulation.
FS/EN (Pin 7)
This is a dual function pin. A resistor placed from FS/EN to ground sets the switching frequency. There is an inverse relationship between the value of the resistor and the switching frequency. This pin can also be used to disable the controller. To disable the controller, pull this pin below 1V.
FB (Pin 8) and COMP (Pin 9)
The internal error amplifier's inverting input and output respectively. These pins are connected to an external R-C network to compensate the regulator.
PGOOD (Pin 25)
Power good. This pin is an open-drain logic signal that indicates when the microprocessor CORE voltage (VSEN pin) is within specified limits and soft-start has timed out.
VCC (Pin 28)
Bias supply voltage for the controller. Connect this pin to a 5V power supply.
4
ISL6219A
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to VCC + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SSOP Package (Note 1) . . . . . . . . . . . . . . . . . . . . . 76 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SSOP - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . -10oC to 85oC
CAUTION: Stress above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief TB379 for details.) Electrical Specifications Parameter INPUT SUPPLY POWER Input Supply Current RT = 100k, FS/EN = 1.23V RT = 100k, FS/EN = 0V Power-On Reset Threshold VCC Rising VCC Falling SYSTEM ACCURACY System Accuracy VID Pull Up VID Input Low Level VID Input High Level (Note 3) OSCILLATOR Accuracy Frequency Adjustment Range Disable Voltage Sawtooth Amplitude Duty-Cycle Range Functional ERROR AMPLIFIER Open-Loop Gain Open-Loop Bandwidth Slew Rate Maximum Output Voltage Minimum Output Voltage ISEN Full Scale Input Current Over-Current Trip Level POWER GOOD MONITOR PGOOD Low Output Voltage PROTECTION and MONITOR IPGOOD = 4mA 0.18 0.4 V 50 75 A A CL=100pF, RL = 10k to ground RL = 10k to ground RL = 10k to ground 3.6 72 18 5.3 4.1 0.23 0.5 dB MHz V/s V V RT = 100k (1%) Guaranteed by design -20 224 100 0 1.23 1.54 280 20 336 1500 1.1 75 % kHz kHz V V % -0.8 2.0 2.5 0.8 0.8 %VID V V V 4.5 4.25 3.75 9.3 8.8 4.38 3.88 15 14 4.5 4.0 mA mA V V Operating Conditions: VCC = 5V, TA = -10oC to 85oC, Unless Otherwise Specified Test Conditions Min Typ Max Units
5
ISL6219A
Electrical Specifications Parameter Overvoltage Threshold VSEN Rising VSEN Falling Undervoltage Threshold VSEN Rising VSEN Falling NOTES: 2. These parts are designed and adjusted for accuracy within the system tolerance given in the Electrical Specifications. The system tolerance accounts for offsets in the differential and error amplifiers; reference-voltage inaccuracies; temperature drift; and the full DAC adjustment range. 3. VID input levels above 2.9V may produce an reference-voltage offset inaccuracy. Use a current limit resistor when pull up to 5V. Operating Conditions: VCC = 5V, TA = -10oC to 85oC, Unless Otherwise Specified (Continued) Test Conditions Min 112 85 80 Typ 115 VID 92 83 Max 12 95 90 Units %VDAC %VDAC %VDAC %VDAC
RC
CC VIN COMP ISL6207 L1
ERROR AMPLIFIER FB
+
PWM CIRCUIT
PWM1
+ +
PWM CIRCUIT ISEN1 RISEN1 VIN PWM CIRCUIT L2
DAC & REFERENCE
+
AVERAGE IOUT
PWM2
ISL6207
VOUT ISEN2 RISEN2 VIN CO P LOAD
RFB
+ ISL6207
+
CURRENT SENSE PWM3
L3
+
CURRENT SENSE
ISL6219A
VSEN
-
CURRENT SENSE
ISEN3 RISEN3
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6219A
6
ISL6219A Operation
Multi-Phase Power Conversion
Multi-phase power conversion provides the most costeffective power solution when load currents are no longer easily supported by single-phase converters. Although its greater complexity presents additional technical challenges, the multi-phase approach offers cost-saving advantages with improved response time, superior ripple cancellation, and excellent thermal distribution. INTERLEAVING The switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels. In a 3-phase converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. As a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. In addition, the peak-topeak amplitude of the combined inductor currents is reduced in proportion to the number of phases (Equations 1 and 2). Increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification.
( V IN - V OUT ) V OUT I L, PP = ----------------------------------------------------L fS V
IN
(EQ. 1)
In Equation 1, VIN and VOUT are the input and output voltages respectively, L is the single-channel inductor value, and fS is the switching frequency.
( V IN - N V OUT ) V OUT I PP = ----------------------------------------------------------L fS V
IN
(EQ. 2)
The output capacitors conduct the ripple component of the inductor current. In the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Compare Equation 1 to the expression for the peak-to-peak current after the summation of N symmetrically phase-shifted inductor currents in Equation 2. Peak-to-peak ripple current decreases by an amount proportional to the number of channels. Output-voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors.
Input-capacitor current, 10A/DIV
IL1 + IL2 + IL3, 7A/DIV
Channel 3 input current 10A/DIV
IL3, 7A/DIV PWM3, 5V/DIV IL2, 7A/DIV PWM2, 5V/DIV IL1, 7A/DIV PWM1, 5V/DIV 1s/div Channel 1 input current 10A/DIV 1s/div Channel 2 input current 10A/DIV
FIGURE 3. CHANNEL INPUT CURRENTS AND INPUTCAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER
FIGURE 2. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 3-PHASE CONVERTER
Figure 2 illustrates the multiplicative effect on output ripple frequency. The three channel currents (IL1, IL2, and IL3), combine to form the AC ripple current and the DC load current. The ripple component has three times the ripple frequency of each individual channel current. Each PWM pulse is terminated 1/3 of a cycle after the PWM pulse of the previous phase. The peak-to-peak current waveforms for each phase is about 7A, and the dc components of the inductor currents combine to feed the load. To understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel's peak-to-peak inductor current.
Another benefit of interleaving is to reduce input ripple current. Input capacitance is determined in part by the maximum input ripple current. Multi-phase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. The example in Figure 3 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. The converter depicted in Figure 3 delivers 36A to a 1.5V load from a 12V input. The rms input capacitor current is 5.9A. Compare this to a single-phase converter also down 12V to 1.5V at 36A. The single-phase converter has 11.9A rms input capacitor current. The single-phase converter
7
ISL6219A
must use an input capacitor bank with twice the rms current capacity as the equivalent three-phase converter. Figures 14 and 15 in the section entitled Input Capacitor Selection can be used to determine the input-capacitor rms current based on load current, duty cycle, and the number of active channels. They are provided as aids in determining the optimal input capacitor solution. Figure 16 shows the single phase input-capacitor rms current for comparisson. PWM OPERATION The number of active channels selected determines the timing for each channel. By default, the timing mode for the ISL6219A is 3-phase. The designer can select 2-phase timing by connecting PWM3 to VCC. One switching cycle for the ISL6219A is defined as the time between PWM1 pulse termination signals (the internal signal that initiates a falling edge on PWM1). The cycle time is the inverse of the switching frequency selected by the resistor connected between the FS/EN pin and ground (see Switching Frequency). Each cycle begins when a clock signal commands the channel-1 PWM output to go low. This signals the channel-1 MOSFET driver to turn off the channel-1 upper MOSFET and turn on the channel-1 synchronous MOSFET. If two-channel operation is selected, the PWM2 pulse terminates 1/2 of a cycle later. If three channels are selected the PWM2 pulse terminates 1/3 of a cycle after PWM1, and the PWM3 output will follow after another 1/3 of a cycle. Once a channel's PWM pulse terminates, it remains low for a minimum of 1/4 cycle. This forced off time is required to assure an accurate current sample as described in Current Sensing. Following the 1/4-cycle forced off time, the controller enables the PWM output. Once enabled, the PWM output transitions high when the sawtooth signal crosses the adjusted error-amplifier output signal, VCOMP as illustrated in Figures 1 and 5. This is the signal for the MOSFET driver to turn off the synchronous MOSFET and turn on the upper MOSFET. The output will remain high until the clock signals the beginning of the next cycle by commanding the PWM pulse to terminate. CURRENT SENSING Intersil multi-phase controllers sense current by sampling the voltage across the lower MOSFET during its conduction interval. MOSFET rDS(ON) sensing is a no-added-cost method to sense current for load-line regulation, channelcurrent balance, module current sharing, and overcurrent protection. If desired, an independent current-sense resistor
I In r DS ( ON ) SEN = I L ------------------------R ISEN VIN CHANNEL N UPPER MOSFET
IL SAMPLE & HOLD + ISEN(n) RISEN I + CHANNEL N LOWER MOSFET ISL6219A INTERNAL CIRCUIT EXTERNAL CIRCUIT r L DS ( ON )
FIGURE 4. INTERNAL AND EXTERNAL CURRENT-SENSING CIRCUITRY
in series with the lower-MOSFET source can serve as a sense element in place of the MOSFET rDS(ON). The ISEN input for each channel uses a ground-referenced amplifier to reproduce a signal proportional to the channel current (Figure 4). After sufficient settling time, the sensed current is sampled, and the sample is used for current balance, load-line regulation and overcurrent protection. The ISL6219A samples channel current once each cycle. Figure 4 shows how the sampled current, In, is created from the channel current IL. The circuitry in Figure 4 represents the current measurement and sampling circuitry for channel n in an N-channel converter. This circuitry is repeated for each channel in the converter but will not be active in unused channels. CHANNEL-CURRENT BALANCE Another benefit of multi-phase operation is the thermal advantage gained by distributing the dissipated heat over multiple devices and greater area. By doing this, the designer avoids the complexity of driving multiple parallel MOSFETs and the expense of using expensive heat sinks and exotic magnetic materials. In order to fully realize the thermal advantage, it is important that each channel in a multi-phase converter be controlled to deliver about the same current at any load level. Intersil multi-phase controllers guarantee current balance by comparing each channel's current to the average current delivered by all channels and making an appropriate adjustment to each channel's pulse width based on the error. Intersil's patented current-balance method is illustrated in Figure 5 where the average of the 2 or 3 sampled channel currents combines with the channel 1 sample, I1, to create an error signal IER. The filtered error signal modifies the pulse width commanded by VCOMP to correct any unbalance and force IER toward zero. In some circumstances, it may be necessary to deliberately design some channel-current unbalance into the system. In a highly compact design, one or two channels may be able
8
ISL6219A
to cool more effectively than the other(s) due to nearby air flow or heat sinking components. The other channel(s) may have more difficulty cooling with comparatively less air flow and heat sinking. The hotter channels may also be located close to other heat-generating components tending to drive their temperature even higher. In these cases, a proper selection of the current sense resistors (RISEN in Figure 4) introduces channel current unbalance into the system. Increasing the value of RISEN in the cooler channels and decreasing it in the hotter channels moves all channels into thermal balance at the expense of current balance. OVERCURRENT PROTECTION The average current, IAVG in Figure 5, is continually compared with a constant 75A reference current. If the average current at any time exceeds the reference current, the comparator triggers the converter to shut down. All PWM signals are placed in a high-impedance state which signals the drivers to turn off both upper and lower MOSFETs. The system remains in this state while the controller counts 2048 phase-clock cycles.
+ + f(j) IER IAVG + PWM1 SAWTOOTH SIGNAL I3 ERROR AMPLIFIER FB + VDROOP I2 I1 IAVG + VCOMP 0V
OUTPUT CURRENT, 20A/DIV
0A
OUTPUT VOLTAGE, 500mV/DIV
5ms/DIV
FIGURE 6. OVERCURRENT BEHAVIOR IN HICCUP MODE
DAC) plus offset errors in the error amplifier. Intersil specifies the guaranteed tolerance of the ISL6219A to include all variations in the amplifiers and reference so that the output voltage remains within the specified system tolerance.
EXTERNAL CIRCUIT RC CC COMP ISL6219A INTERNAL CIRCUIT
VCOMP
/N
RFB
REFERENCE VOLTAGE(VDAC)
VSEN VOUT
FIGURE 5. CHANNEL-1 PWM FUNCTION AND CURRENTBALANCE ADJUSTMENT
This is followed by a soft-start attempt (see Soft-Start). If the soft-start attempt is successful, operation will continue as normal. Should the soft-start attempt fail, the ISL6219A repeats the 2048-cycle wait period and follows with another soft-start attempt. This hiccup mode of operation continues indefinitely as shown in Figure 6 as long as the controller is enabled or until the overcurrent condition resolves. VOLTAGE REGULATION The ISL6219A uses a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at pins VID4 to VID0. The DAC decodes the a 5-bit logic signal (VID) into one of the discrete voltages shown in Table 1. Each VID input offers a 20A pull up to 2.5V for use with open-drain outputs. External pull-up resistors or active-high output stages can augment the pull-up current sources, but a slight accuracy error can occur if they are pulled above 2.9V. The integrating compensation network shown in Figure 7 assures that the steady-state error in the output voltage is limited to the error in the reference voltage (output of the
FIGURE 7. OUTPUT-VOLTAGE AND LOAD-LINE REGULATION
TABLE 1. VOLTAGE IDENTIFICATION CODES VID4 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 VID1 1 1 0 0 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 0 1 0 1 VDAC Off 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325
9
ISL6219A
TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued) VID4 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDAC 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850
LOAD-LINE REGULATION In applications with high transient current slew rates, the lowest-cost solution for maintaining regulation often requires some kind of controlled output impedance. A current proportional to the average current of all active channels is steered into the inverting input of the error amplifier. There is no DC return path connected to the FB pin except for the feedback resistor, RFB. Therefore, the average current, IAVG, produces a voltage drop across the feedback resistor, RFB, proportional to the output current. In Figure 7, the steady-state value of VDROOP is simply
V DROOP = I AVG R FB (EQ. 3)
In the case that each channel uses the same value for RISEN to sense channel current, a more complete expression for VDROOP can be determined from the expression for IAVG as it is derived from Figures 4 and 5.
I OUT I AVG = ------------N I OUT V DROOP = ------------N r DS ( ON ) ---------------------R ISEN r DS ( ON ) ---------------------- R FB R ISEN
(EQ. 4)
ENABLE AND DISABLE Three separate input conditions must be met before the ISL6219A is released from shut-down mode. The PWM outputs are held in a high-impedance state to assure the drivers remain off during shut-down. The internal power-on reset circuit (POR) prevents the ISL6219A from starting before the bias voltage at VCC reaches the POR-rising threshold as defined in Electrical Specifications. The rising threshold is high enough to guarantee that all parts of the ISL6219A can perform their functions properly. There is enough hysteresis in the PORfalling threshold to prevent nuisance tripping.
VCC 1.23V EXTERNAL CIRCUIT
OVERVOLTAGE PROTECTION If the ISL6219A detects output voltages above 115% of VID, the controller will immediately commands all PWM outputs low. This directs the Intersil drivers to turn on the lower MOSFETs and protect the load by preventing any further increase in output voltage. Once the output voltage falls to the level set by the VID code, the PWM outputs enter highimpedance mode. The Intersil drivers respond by turning off both upper and lower MOSFETs. If the overvoltage condition reoccurs, the ISL6219A will again command the lower MOSFETs to turn on. The ISL6219A will continue to protect the load in this fashion as long as the overvoltage repeats. After detecting an overvoltage condition, the ISL6219A terminates normal PWM operation until it is reset by one of two methods. Either by pulling VCC below the POR falling threshold and restoring it above the POR rising threshold or cycling FS/EN.
+ -
+
FS/EN S1
ENABLE SIGNAL
FIGURE 8. EXTERNAL ENABLE SIGNAL CIRCUIT
Under-Voltage
The VSEN pin also detects when the CORE voltage drops below the VID programmed under-voltage falling threshold. This causes PGOOD to go low, but has no other effect on operation and is not latched. The frequency select/enable input (FS/EN) has a 1V threshold which must be exceeded before the internal oscillator begins running. An external enable signal should be used to control the gate of an external MOSFET tied to the FS/EN pin, see Figure 8. This MOSFET must pull FS/EN below the 1V threshold to disable the controller. When enabling the controller, this
10
ISL6219A
external enable circuit must release the FS/EN pin to float to the designed 1.23V level. The 11111 VID code is reserved as a signal to the controller that no load is present. The controller will enter shut-down mode after receiving this code and will start up upon receiving any other code. To enable the controller, VCC must be greater than the POR threshold; FS/EN must be greater than 1V; and VID cannot be equal to 11111. Once these conditions are true, the controller immediately initiates a soft start sequence. SOFT-START After the POR function is completed with VCC reaching 4.38V, the soft-start sequence is initiated. Soft-Start, by its slow rise of CORE voltage from zero, avoids an over-current condition by slowly charging the output capacitors. This voltage rise is initiated by an internal DAC that slowly raises the reference voltage to the error amplifier input. The voltage rise is controlled by the oscillator frequency and the DAC within the controller, therefore, the output voltage is effectively regulated as it rises to the final programmed CORE voltage value. For the first 32 PWM switching cycles, the DAC output remains inhibited and the PWM outputs remain in a highimpedance state. From the 33rd cycle and for another, approximately 150 cycles the PWM output remains low, clamping the lower output MOSFETs to ground. The time variability is due to the error amplifier, sawtooth generator and comparators moving into their active regions. After this short interval, the PWM outputs are enabled and increment the PWM pulse width from zero duty cycle to operational pulse width, thus allowing the output voltage to slowly reach the CORE voltage. The CORE voltage will reach its programmed value before the 2048 cycles, but the PGOOD output will not be initiated until the 2048th PWM switching cycle. The soft-start time, tSS, is determined by an 11-bit counter that increments with every pulse of the phase clock. For example, a converter switching at 300kHz has a soft-start time of
2048 2 11 T SS = --------- = -------------------- = 6.8ms 300kHz f SW (EQ. 5)
1.5V
FS/EN, 2V/div 0V PGOOD, 5V/div 0V 1ms/div
SS Interval
VCOMP, 1V/div 0V
VCORE, 1V/div 0V
FIGURE 9. START-UP OF 3 PHASE SYSTEM OPERATING AT 300kHz
another full cycle, the ISL6219A begins incrementing the reference by making 25mV change every two switching cycles until it reaches the new VID code. Since the ISL6219A recognizes VID-code changes only at the beginning of a switching cycle, up to one full cycle may pass before a VID change registers. This is followed by a one-cycle wait before the output voltage begins to change. Thus, the total time required for a VID change, tDV, is dependent on the switching frequency (fS), the size of the change (VID), and the time before the next switching cycle begins. The one-cycle uncertainty in Equation 6 is due to the possibility that the VID code change may occur up to one full cycle before being recognized. The time required for a converter running with fS = 500kHz to make a 1.5V to 1.7V reference-voltage change is between 30s and 32s as calculated using Equation 6. This example is also illustrated in Figure 10.
01110 00110 VID, 5V/div VID CHANGE OCCURS ANYWHERE HERE
VREF, 100mV/div
Figure 9 shows the waveforms when the regulator is operating at 300kHz. Note that the soft-start duration is a function of the Channel Frequency as explained previously. DYNAMIC VID The ISL6219A is capable of executing on-the-fly outputvoltage changes. At the beginning of the phase-1 switching cycle (defined in the section entitled PWM Operation), the ISL6219A checks for a change in the VID code. The VID code is the bit pattern present at pins VID4-VID0 as outlined in Voltage Regulation. If the new code remains stable for
VOUT, 100mV/div 1.5V
5s/div
FIGURE 10. DYNAMIC-VID WAVEFORMS FOR 500KHz ISL6219A BASED MULTI-PHASE BUCK CONVERTER
.
11
ISL6219A
1 2 V ID 1 2 V ID ---- ---------------- - 1 < t DV ---- ---------------- f S 0.025 f S 0.025
(EQ. 6)
the beginning and the end of the lower-MOSFET conduction interval respectively.
I M I PP IM I P LOW , 2 = V D ( ON ) f S ----- + -------- t - d1 + ----- - -------- t d2 - PP 2 2 N N (EQ. 8)
General Design Guide
This design guide is intended to provide a high-level explanation of the steps necessary to create a multi-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced below. In addition to this guide, Intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications.
Thus the total power dissipated in each lower MOSFET is approximated by the summation of PL and PD. UPPER MOSFET POWER CALCULATION In addition to rDS(ON) losses, a large portion of the upperMOSFET losses are due to currents conducted across the input voltage (VIN) during switching. Since a substantially higher portion of the upper-MOSFET losses are dependant on switching frequency, the power calculation is somewhat more complex. Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times; the lower-MOSFET body-diode reverserecovery charge, Qrr; and the upper MOSFET rDS(ON) conduction loss. When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 9, the required time for this commutation is t1and the associated power loss is PUP,1.
I M I L ,PP t 1 P UP,1 V IN ----- + ------------ ---- f S 2 2 N (EQ. 9)
Power Stages
The first step in designing a multi-phase converter is to determine the number of phases. This determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted on either side; and the total board space available for powersupply circuitry. Generally speaking, the most economical solutions will be for each phase to handle between 15 and 20A. All-surface-mount designs will tend toward the lower end of this current range and, if through-hole MOSFETs can be used, higher per-phase currents are possible. In cases where board space is the limiting constraint, current can be pushed as high as 30A per phase, but these designs require heat sinks and forced air to cool the MOSFETs.
MOSFETs
The choice of MOSFETs depends on the current each MOSFET will be required to conduct; the switching frequency; the capability of the MOSFETs to dissipate heat; and the availability and nature of heat sinking and air flow. LOWER MOSFET POWER CALCULATION The calculation for heat dissipated in the lower MOSFET is simple, since virtually all of the heat loss in the lower MOSFET is due to current conducted through the channel resistance (rDS(ON)). In Equation 7, IM is the maximum continuous output current; IL,PP is the peak-to-peak inductor current (see Equation 1); d is the duty cycle (VOUT/VIN); and L is the per-channel inductance.
I L ,PP ( 1 - d ) I M 2 P LOW ,1 = r DS ( ON ) ----- ( 1 - d ) + ------------------------------12 N
2
Similarly, the upper MOSFET begins conducting as soon as it begins turning on. In Equation 10, this transition occurs over a time t2, and the approximate the power loss is PUP,2.
I M I L ,PP t 2 P UP, 2 V IN ----- - ------------- ---- f S 2 2 N (EQ. 10)
A third component involves the lower MOSFET's reverserecovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lowerMOSFET's body diode can recover all of Qrr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is PUP,3 and is simply
P UP,3 = V IN Q rr f S (EQ. 11)
(EQ. 7)
An additional term can be added to the lower-MOSFET loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-MOSFET body diode. This term is dependent on the diode forward voltage at IM, VD(ON); the switching frequency, fS; and the length of dead times, td1 and td2, at
Finally, the resistive part of the upper MOSFET's is given in Equation 12 as PUP,4.
2 2 I PP I M P UP,4 = r DS ( ON ) ----- d + --------12 N
(EQ. 12)
In this case, of course, rDS(ON) is the on resistance of the upper MOSFET.
12
ISL6219A
The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 9, 10, 11 and 12. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process that involves repetitively solving the loss equations for different MOSFETs and different switching frequencies until converging upon the best solution.
V DROOP R FB = -------------------------------I FL r DS ( ON )
R ISEN ( n )
n
(EQ. 16)
Compensation
The two opposing goals of compensating the voltage regulator are stability and speed. Depending on whether the regulator employs the optional load-line regulation as described in Load-Line Regulation, there are two distinct methods for achieving these goals. COMPENSATING A LOAD-LINE REGULATED CONVERTER The load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter L-C resonant frequency split with the introduction of current information into the control loop. The final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, RC and CC. Since the system poles and zero are effected by the values of the components that are meant to compensate them, the solution to the system equation becomes fairly complicated. Fortunately there is a simple approximation that comes very close to an optimal solution. Treating the system as though it were a voltage-mode regulator by compensating the L-C poles and the ESR zero of the voltage-mode approximation yields a solution that is always stable with very close to ideal transient performance.
C2 (OPTIONAL)
Current Sensing
Pins 23, 20 and 19 are the ISEN pins denoted ISEN1, ISEN2 and ISEN3 respectively. The resistors connected between these pins and the phase nodes determine the gains in the load-line regulation loop and the channel-current balance loop. Select the values for these resistors based on the room temperature rDS(ON) of the lower MOSFETs; the full-load operating current, IFL; and the number of phases, N according to Equation 13 (see also Figure 4).
r DS ( ON ) R ISEN = ----------------------50 x10- 6 I FL ------N (EQ. 13)
In certain circumstances, it may be necessary to adjust the value of one or more of the ISEN resistors. This can arise when the components of one or more channels are inhibited from dissipating their heat so that the affected channels run hotter than desired (see the section entitled Channel-Current Balance). In these cases, chose new, smaller values of RISEN for the affected phases. Choose RISEN,2 in proportion to the desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase.
T 2 R ISEN ,2 = R ISEN ---------T
1
(EQ. 14)
RC CC
In Equation 14, make sure that T2 is the desired temperature rise above the ambient temperature, and T1 is the measured temperature rise above the ambient temperature. While a single adjustment according to Equation 14 is usually sufficient, it may occasionally be necessary to adjust RISEN two or more times to achieve perfect thermal balance between all channels.
COMP
+ RFB VDROOP VSEN
Load-Line Regulation Resistor
The load-line regulation resistor is labeled RFB in Figure 7. Its value depends on the desired full-load droop voltage (VDROOP in Figure 7). If Equation 13 is used to select each ISEN resistor, the load-line regulation resistor is as shown in Equation 15.
V DROOP R FB = ------------------------6 50 x10 (EQ. 15)
FIGURE 11. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6219A CIRCUIT
If one or more of the ISEN resistors was adjusted for thermal balance as in Equation 14, the load-line regulation resistor should be selected according to Equation16 where IFL is the full-load operating current and RISEN(n) is the ISEN resistor connected to the nth ISEN pin.
The feedback resistor, RFB, has already been chosen as outlined in Load-Line Regulation Resistor. Select a target bandwidth for the compensated system, f0. The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. The values of the compensation components depend on the relationships of f0 to the L-C pole frequency and the ESR zero frequency. For each of the three cases
13
ISL6219A
FB
ISL6219A
defined below, there is a separate set of equations for the compensation components. Case 1:
1 ------------------- > f 0 2 LC 2f 0 V pp LC R C = R FB ----------------------------------0.75V IN 0.75V IN C C = ----------------------------------2V PP R FB f 0
RC
III controller, as shown in Figure 12, provides the necessary compensation.
C2
CC
COMP
FB C1 R1 RFB
Case 2:
1 1 ------------------- f 0 < ----------------------------2C ( ESR ) 2 LC V PP ( 2 ) f 0 LC R C = R FB -------------------------------------------0.75 V
IN 2 2
+
VDROOP
VSEN
(EQ. 17)
0.75V IN C C = -----------------------------------------------------------( 2 ) 2 f 02 V PP R FB LC
Case 3:
1 f 0 > ----------------------------2C ( ESR ) 2 f 0 V pp L R C = R FB ----------------------------------------0.75 V IN ( ESR ) 0.75V IN ( ESR ) C C C = -----------------------------------------------2V PP R FB f 0 L
FIGURE 12. COMPENSATION CIRCUIT FOR ISL6219A BASED CONVERTER WITHOUT LOAD-LINE REGULATION.
In Equations 17, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and VPP is the peak-to-peak sawtooth signal amplitude as described in Figure 5 and Electrical Specifications. Once selected, the compensation values in Equations 17 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to RC. Slowly increase the value of RC while observing the transient performance on an oscilloscope until no further improvement is noted. Normally, CC will not need adjustment. Keep the value of CC from Equations 17 unless some performance issue is noted. The optional capacitor C2, is sometimes needed to bypass noise away from the PWM comparator (see Figure 5). Keep a position available for C2, and be prepared to install a highfrequency capacitor of between 22pF and 150pF in case any jitter problem is noted. COMPENSATION WITHOUT LOAD-LINE REGULATION The non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the L-C resonant frequency and a zero at the ESR frequency. A type
The first step is to choose the desired bandwidth, f0, of the compensated system. Choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. The type-III compensator has an extra high-frequency pole, fHF. This pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. A good general rule is to chose fHF = 10 f0, but it can be higher if desired. Choosing fHF to be lower than 10 f0 can cause problems with too much phase shift below the system bandwidth. In the solutions to the compensation equations, there is a single degree of freedom. For the solutions presented in Equations 18, RFB is selected arbitrarily. The remaining compensation components are then selected according to Equations 18.
LC - C ( ESR ) C 1 = ---------------------------------------R FB V PP 2 f 0 f HF LC R C = --------------------------------------------------------------------2 f HF LC - 1 0.75 V IN C ( ESR ) R 1 = R FB ---------------------------------------LC - C ( ESR ) 0.75V IN C 2 = -----------------------------------------------------------------( 2 ) 2 f 0 f HF LCR FB V PP 0.75V IN C C = -------------------------------------------------------------------------------- 1 2V PP R f 0 1 - ---------------------------- FB 2f HF LC (EQ. 18)
2
14
ISL6219A
ISL6219A
In Equations 18, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent-series resistance of the bulk output-filter capacitance; and VPP is the peak-to-peak sawtooth signal amplitude as described in Figure 5 and "Electrical Specifications". source the inductor ac ripple current (see Interleaving and Equation 2), a voltage develops across the bulk-capacitor ESR equal to IPP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the a lower limit on the inductance.
V - N V OUT V OUT IN L ( ESR ) ----------------------------------------------------------f S V IN V PP( MAX ) (EQ. 20)
Output Filter Design
The output inductors and the output capacitor bank together form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy during the interval of time after the beginning of the transient until the regulator can fully respond. Because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response leaving the output capacitor bank to supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, I; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total outputvoltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount
di V ( ESL ) ---- + ( ESR ) I dt (EQ. 19)
Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than VMAX. This places an upper limits on inductance.
2NCVO L -------------------- V MAX - I ( ESR ) ( I ) 2 (EQ. 21)
( 1.25 ) NC L ------------------------- V MAX - I ( ESR ) V IN - V O ( I ) 2
(EQ. 22)
Equation 22 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater outputvoltage deviation than the leading edge. Equation 21 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels.
Switching Frequency
There are a number of variables to consider when choosing the switching frequency. There are considerable effects on the upper-MOSFET loss calculation and, to a lesser extent, the lower-MOSFET loss calculation. These effects are outlined in MOSFETs, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small outputvoltage ripple as outlined in Output Filter Design. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. Switching frequency is determined by the selection of the frequencysetting resistor, RT (see the figure Typical Application on page 3). Figure 13 and Equation 23 are provided to assist in the selecting the correct value for RT.
RT = 10
[11.09 - 1.13 log ( f S ) ]
The filter capacitor must have sufficiently low ESL and ESR so that V < VMAX. Most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and
(EQ. 23)
Input Capacitor Selection
The input capacitors are responsible for sourcing the ac component of the input current flowing into the upper MOSFETs. Their rms current capacity must be sufficient to handle the ac component of the current drawn by the upper
15
ISL6219A
1000 0.3 INPUT-CAPACITOR CURRENT (IRMS / IO)
IPP = 0 IPP = 0.25 IO
IPP = 0.5 IO IPP = 0.75 IO
RT (k)
0.2
100
0.1
10
10
100 1000 SWITCHING FREQUENCY (KHZ)
10000 0 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VIN / VO)
FIGURE 13. RT VS SWITCHING FREQUENCY
MOSFETs which is related to duty cycle and the number of active phases. Figures 14 and 15 can be used to determine the inputcapacitor rms current as of duty cycle, maximum sustained output current (IO), and the ratio of the combined peak-topeak inductor current (IL,PP) to IO. Figure 16 is provided as a reference to demonstrate the dramatic reductions in inputcapacitor rms current upon the implementation of the multiphase topology.
0.3 INPUT-CAPACITOR CURRENT (IRMS / IO)
FIGURE 15. NORMALIZED INPUT-CAPACITOR RMS CURRENT VS DUTY CYCLE FOR 3-PHASE
0.6 INPUT-CAPACITOR CURRENT (IRMS / IO)
0.4
0.2
IPP = 0 IPP = 0.5 IO IPP = 0.75 IO
0 0 0.2 0.4 0.6 DUTY CYCLE (VIN / VO) 0.8 1.0
0.2
0.1
IPP = 0 IPP = 0.5 IO IPP = 0.75 IO
0 0 0.2 0.4 0.6 0.8 1.0
FIGURE 16. NORMALIZED INPUT-CAPACITOR RMS CURRENT VS DUTY CYCLE FOR SINGLE-PHASE CONVERTER
DUTY CYCLE (VO /VIN)
FIGURE 14. NORMALIZED INPUT-CAPACITOR RMS CURRENT VS DUTY CYCLE FOR 2-PHASE
16
ISL6219A Shrink Small Outline Plastic Packages (SSOP)
N INDEX AREA E -B1 2 3 L SEATING PLANE -AD -CA 0.25 0.010 h x 45o GAUGE PLANE H 0.25(0.010) M BM
M28.15
28 LEAD SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D MIN 0.053 0.004 0.008 0.007 0.386 0.150 MAX 0.069 0.010 0.061 0.012 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.20 0.18 9.81 3.81 MAX 1.75 0.25 1.54 0.30 0.25 10.00 3.98 NOTES 9 3 4 5 6 7 8o Rev. 0 2/95
A1 0.10(0.004) A2 C
E e H h L N
e
B 0.17(0.007) M C AM BS
0.025 BSC 0.228 0.0099 0.016 28 0o 8o 0.244 0.0196 0.050
0.635 BSC 5.80 0.26 0.41 28 0o 6.19 0.49 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
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For information regarding Intersil Corporation and its products, see www.intersil.com 17

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